Interactive simulation
Transmission line simulation
A step launched into a mismatched trace, bouncing until it settles — why a short track suddenly matters.
A PCB trace is a delay line: 150 mm of track holds the edge for a full nanosecond before the far end hears about it. The driver cannot know what the load is yet, so it launches Z0/(Z0+Zs) of its swing into the line, and the mismatch at the far end sends ΓL = (ZL−Z0)/(ZL+Z0) of that straight back. What returns bounces again off the driver with ΓS = (Zs−Z0)/(Zs+Z0), and it is their product that tells the story — the quantity printed on the sketch: negative ΓS·ΓL rings and overshoots, positive ΓS·ΓL climbs the slow staircase, and Zs = Z0 — series termination — kills every echo after the first. The sign of ΓS alone is not the rule: below Z0 the load flips ΓL too, and the shape flips back. Now slow the edge down. Once tr is longer than the 2·Td round trip the reflections fold back into the edge and the trace stops mattering, which is exactly why the layout that was fine last year is not fine at today's slew rate.
What you can change
- Load ZL
