Interactive simulation
UART frame simulation
One byte on a wire that carries no clock — and the receiver's own timer walking off the bit centres.
Nothing on this wire carries a clock. The receiver starts its own timer on the falling edge of the start bit and samples the middle of each cell with its own bit period Tr = Tb / (1 + e); the slip against the transmitter is (n + ½)·Tb·e / (1 + e), so it grows with the bit number and it is always the stop bit that breaks first. Past roughly ±5 % the ticks drop into the neighbouring cell and the decoded byte changes — but only a receiver running fast reports it. Run slow and the stop sample walks forward past the stop bit into the idle line, which is also high, so the stop bit still reads 1: the byte is corrupted in silence, with no framing error to catch it. That asymmetry is why a slow receiver is the harder fault to find. Bytes like 0x00 and 0xFF survive far larger errors, because the cell next door happens to hold the same value.
