Pinout
USB Type-C (USB-PD capable receptacle) pinout
Pins
- A4/B4, A9/B9 — VBUS: four pins tied to one net, not four separate rails, so the current is split across more contact area; sits at a fixed 5V by default and only rises once a PD contract is actually negotiated over CC.
- A1/B1, A12/B12 — GND: the return path for VBUS and for both SuperSpeed pairs, likewise duplicated across four pins for current capacity, not wired as separate grounds.
- A5 — CC1, B5 — CC2: only whichever pin actually mates carries the Configuration Channel (the other is left floating or becomes VCONN — see below). Its DC level, set by an Rd/Rp resistor pair, is how the two ends first sense that something is even plugged in and which side is the power source, before any data moves.
- That same mated CC pin then carries the actual USB-PD protocol: Biphase Mark Coded (BMC) messages at a nominal 300 kb/s (±10%), built from a preamble, a message header, a data payload and a CRC — a real serial link, not a DC level, so a multimeter on CC only ever shows the idle Rp/Rd voltage and never the negotiation traffic.
- The CC pin that did NOT mate becomes VCONN whenever a cable needs it — an electronically-marked ("e-marked") cable, any USB 3.x/4 cable, or any link sourcing over 3A: the source or sink switches roughly 5V onto it, spec’d at a minimum of 1W (about 200mA) to run the cable’s ID chip and any signal redrivers inside it.
- A6/A7 and B6/B7 — two mirrored USB 2.0 D+/D− pairs; only one pair is actually driven per insertion, selected by which CC line mated. The second pair exists purely so the plug works either way up, not to add bandwidth.
- A2/A3+A10/A11 and B2/B3+B10/B11 — SSTX/SSRX SuperSpeed differential pairs (USB 3.x); same reasoning as D+/D−, only one full A-side or B-side set is live per orientation.
- A8/B8 — SBU1/SBU2: idle on plain USB and on PD itself, these are handed to an Alt Mode’s sideband channel (e.g. DisplayPort’s AUX line) once a Vendor-Defined Message negotiated over CC puts the port into that mode.
Specifications
| Contacts | 24 (receptacle) |
|---|---|
| Default VBUS | 5 V until a PD contract is negotiated |
| PD fixed voltages (SPR) | 5, 9, 15, 20 V |
| PD fixed voltages (EPR, PD 3.1) | 28, 36, 48 V |
| Max current | 3 A; 5 A with a 5 A e-marked cable |
| Max power | 100 W (SPR, 20 V × 5 A), 240 W (EPR, 48 V × 5 A) |
| PPS (PD 3.0) | 3.3–21 V in 20 mV steps |
| Negotiation | BMC on CC, 300 kbit/s |
| VCONN | 5 V, at least 1 W, for e-marked cables |
| Sink trigger ICs | STUSB4500, CH224, IP2721, FUSB302 |
Notes
- A bare USB-C connection only ever guarantees 5V. Every higher "Standard Power Range" step (9V, 15V, 20V, and 12V on some chargers) and every "Extended Power Range" step added in PD 3.1 (28V, 36V, 48V, up to 5A/240W) is something the sink must explicitly request and the source must grant over the CC data protocol — there is no resistor trick that produces 9V+ the way some proprietary fast-charge schemes manage without real PD.
- A device that only pulls CC down through a fixed 5.1 kΩ Rd, with no PD logic behind it, still gets power (this is plain "USB Type-C Current," capped at 5V/3A ≈15W by whichever pull-up value the source chose) — but it will never see anything above 5V, because there is nothing there to run the BMC handshake.
- To pull more than 5V out of a PD charger without writing your own USB-PD stack, use a dedicated PD sink/trigger IC that runs the CC negotiation for you (e.g. STUSB4500, CH224, IP2721, FUSB302) and exposes a simple pin-strap or I2C interface to request a fixed voltage once it reports a contract is in place.
- A source only ever offers the PDOs it actually implements — a basic 5W/10W charger may stop at 5V or 9V, while a laptop charger may go up to 20V or, on newer EPR chargers, 48V — so check its advertised Source_Capabilities rather than assuming every "PD charger" reaches every voltage.
- VBUS and GND being spread across four pins each is a current-capacity and contact-resistance measure, not four independent nets — for example, do not treat A9’s VBUS as separately switchable from A4’s.
