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A UART divides the MCU clock by an integer: $\mathrm{divisor}=\mathrm{round}\left(\frac{f_{\mathrm{clk}}}{\mathrm{OSR}\times \mathrm{baud}}\right)$, where OSR is the oversampling factor chosen below. That rounding is the whole source of the error: under ~2% total is fine, past ~3.5% frames start corrupting — which is why 115200 from an 8 MHz part misbehaves.

The port then runs at ${\mathrm{baud}}_{\mathrm{real}}=\frac{f_{\mathrm{clk}}}{\mathrm{OSR}\times \mathrm{divisor}}$, and the Error column is $\mathrm{error}=\frac{{\mathrm{baud}}_{\mathrm{real}}-\mathrm{baud}}{\mathrm{baud}}\times 100\text{\%}$. The divisor is never taken below 1, so a clock too slow for the rate lands as a large negative error rather than a division by zero.

With the clock as read: $\mathrm{divisor}=\mathrm{round}\left(\frac{16\text{MHz}}{16\times \mathrm{baud}}\right)$