مخطط الأطراف
مخطط أطراف العداد العشري CD4017 (DIP-16)
الأطراف
- 14 CLK (counts on rising edge)
- 13 CLOCK INHIBIT / EN (tie LOW to count)
- 15 RESET (HIGH forces Q0)
- Outputs in order: 3 Q0, 2 Q1, 4 Q2, 7 Q3, 10 Q4, 1 Q5, 5 Q6, 6 Q7, 9 Q8, 11 Q9 — one HIGH at a time
- 12 CO (carry out — ÷10 clock for the next stage)
- 16 VDD (3–15V), 8 VSS (GND)
المواصفات
| Logic family | CD4000 series CMOS |
|---|---|
| جهد التغذية | 3–18 V |
| Max clock frequency | ≈ 5 MHz typ at 10 V (lower at 5 V) |
| Outputs | 10 decoded outputs (one HIGH at a time) + carry out (÷10) |
| Output current | Weak: ≈ 0.5 mA min sink at 5 V, 1.3 mA at 10 V |
| Clock input | Schmitt-triggered |
| Quiescent current | 5 µA max at 5 V, 25 °C |
| Operating temperature | −55–125 °C |
| الغلاف | DIP-16, SOIC-16 |
