مخطط الأطراف

مخطط أطراف مسجل إزاحة بإدخال متوازٍ 74HC165 (DIP-16)

الأطراف

1: SH/LD (Shift/Load — active LOW loads the 8 parallel inputs; HIGH shifts on CLK)
2: CLK (shift clock, rising edge)
3: E
4: F
5: G
6: H (parallel inputs — H is the bit that comes out first)
7: /QH (complementary serial output)
8: GND
9: QH (serial output — to the MCU, or to the next chip's SER)
10: SER (serial input, for daisy-chaining — feed the previous chip's QH in here)
11: A
12: B
13: C
14: D (parallel inputs)
15: CLK INH (clock inhibit — hold LOW to let CLK act; HIGH freezes the register regardless of CLK)
16: VCC

Logic family	74HC (high-speed CMOS)
Function	8-bit parallel-in, serial-out (QH plus inverted QH output)
جهد التغذية	2–6 V
Input levels at 4.5 V	HIGH ≥ 3.15 V, LOW ≤ 1.35 V
Output current	±4 mA specified at 4.5 V
Quiescent current	8 µA max at 25 °C
Cascading	QH of one chip into SER (pin 10) of the next
الغلاف	DIP-16, SOIC-16, TSSOP-16

The read side of the 74HC595 above: 595 turns serial data into parallel outputs, 165 turns 8 parallel inputs into a serial stream — pair them for a cheap way to add many buttons/switches to a microcontroller with only 3 signal pins.
The eight inputs are not in one row: E–H sit on pins 3–6 and A–D across the chip on pins 11–14, with the serial pins between them — wiring them as 1-to-8 down one side is the classic mistake with this part.
The parallel inputs are named A–H, not D0–D7 — that is this chip family's own datasheet convention, not a different bit-order. Relabeling them D0–D7 in your own notes is fine as long as you keep A=D0...H=D7 consistent end to end.
CLK INH is usually just tied LOW (always enabled) in a single-chip design; it earns its keep when daisy-chaining several 165s off one shared CLK/SH-LD pair, letting one chip's clock be gated off without disturbing the others.