مخطط الأطراف

مخطط أطراف مسجل الإزاحة 74HC595 (DIP-16)

الأطراف

14 SER (serial data in)
11 SRCLK (shift clock)
12 RCLK (latch clock)
13 OE (output enable, active low)
10 SRCLR (clear, active low — tie to VCC)
15 QA, 1–7 QB–QH (parallel outputs)
9 QH' (serial out — chains the next chip)
16 VCC, 8 GND

المواصفات

Logic family	74HC (high-speed CMOS)
Function	8-bit serial-in, parallel-out with output latch and 3-state outputs
جهد التغذية	2–6 V
Input levels at 4.5 V	HIGH ≥ 3.15 V, LOW ≤ 1.35 V
Output current	±6 mA specified per output at 4.5 V; ±35 mA absolute max per pin, ±70 mA total VCC/GND
Max clock frequency	25 MHz guaranteed at 4.5 V (TI)
Quiescent current	8 µA max at 25 °C
Cascading	QH' (pin 9) feeds SER of the next chip
الغلاف	DIP-16, SOIC-16, TSSOP-16

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