Simulation interactive

Temps de montée I2C

La résistance de tirage doit charger chaque picofarad du bus — regardez le front perdre la course contre l'horloge.

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An open-drain pin can only pull down; the only thing pulling the line back up is Rp, so every rising edge is the RC charge of the whole bus capacitance: V(t) = Vdd − (Vdd − VOL)·e^(−t/RpCb). The spec measures it between 0.3 and 0.7 Vdd, which makes tr = Rp·Cb·ln(7/3) = 0.847·Rp·Cb — 1 µs allowed in standard mode, 300 ns in fast mode, 120 ns in fast-mode plus. Add devices (Cb grows about 10 pF a chip, plus the wiring) and the edge stops reaching VIH = 0.7 Vdd before the clock falls again: the red part of the trace is time the bus spends at no valid level at all. Answering with a smaller Rp is not free — the pin holding the line low then sinks Vdd/(Rp + Ron), and I2C only guarantees 3 mA at 0.4 V. The driver's own 40 Ω is what sets VOL = Vdd·Ron/(Ron + Rp). The clock here is drawn at 50 % duty, which is already kinder than the spec's own tHIGH minimum — a real fast-mode bus only holds SCL high for 0.6 µs of its 2.5 µs period.