Simulation interactive
Registre à décalage
Huit bits défilent dans le 74HC595 — mais les broches ne bougent pas avant l'impulsion du latch.
Two registers, two clocks. Every rising edge of SHCP shifts the whole chain one place — QH←QG … QA←DS — and pushes the oldest bit off the end towards the next chip, which sampled it on QH′ just before that edge. QH′ itself is only a buffered copy of the eighth stage, so it always reads exactly what QH reads. The eight pins do not follow that chain: they show the storage register, which copies the shift register only on a rising edge of STCP. Switch to Never latch and clock a byte in — the top row marches, the LEDs stay exactly where they were. That is the bug people lose an evening to. Because shiftOut() sends the MSB first, the first bit ends up in QH, so the byte reads QH…QA, right to left across the pins. SRCLR is active low and clears the shift register alone; the pins hold their last latched value.
