Simulación interactiva
Contador asíncrono
Cuatro biestables dividiendo por dos, y los números erróneos que muestran los pines entretanto.
Nothing here is clocked together. The input edge reaches stage 0 only; stage 1 waits for Q0 to fall, stage 2 for Q1, stage 3 for Q2, so the answers arrive at t_pd, 2·t_pd, 3·t_pd and 4·t_pd — watch the orange dot walk down the chain. During that window the four pins hold a number that is neither the old count nor the new one: at the eighth edge 0111 passes through 0110, 0100 and 0000 on its way to 1000, and anything decoding those pins sees three false hits. The red band on the count trace is exactly that window. Raise the frequency or the delay until 4·t_pd fills a whole period and even the worst edge — all four bits flipping at once — can no longer finish settling before the next edge arrives: a clean decode at EVERY edge needs T > 4·t_pd, i.e. f < 1/(4·t_pd). That edge is only 1 in 16 though — the rest flip one, two or three bits and settle inside a shorter window — so the count keeps returning to valid between glitches well past that limit; it stops being GUARANTEED clean there, not valid altogether. Switch to Synchronous: one clock for all four flip-flops, every bit moves at t_pd together, so the pins are only ever one t_pd behind — late, never wrong. That is what the extra steering gates are for.
